EP1S80F1020C7 vs EP1S80F1020C5N Comparaison
Comparaison détaillée côte à côte de EP1S80F1020C7 par Altera et EP1S80F1020C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S80F1020C7 | EP1S80F1020C5N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Fin de vie |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $195,00 | $0,00 |
| Series | Stratix | — |
| Logic Elements | 79,040 | 79,040 |
| System Gates (typical) | 7,427,520 | — |
| Logic Array Blocks (LABs) | 7,904 | — |
| User I/O Pins | 773 | 773 I/O |
| Total Package Pins | 1020 (ball) | — |
| Package Type | FBGA-1020 (33 x 33 mm, 1 mm pitch) | FBGA-1020 |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V | — |
| Température de fonctionnement | 0 C to 85 C (Commercial) | 0 °C to 85 °C |
| Logic Family | CMOS, SRAM-based configuration | — |
| Process Technology | 1.5 V, 0.13 um CMOS | — |
| Configuration Modes | Passive Serial (PS), Fast Passive Parallel (FPP), JTAG | — |
| PLLs | 12 (per datasheet family) | — |
| Memory | TriMatrix embedded SRAM blocks | — |
| DSP Blocks | Dedicated hardware multipliers/accumulators | — |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | Compliant (lead-free FBGA) | unknown |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | Stratix |
| Logic Technology | — | CMOS |
| Logic Cells | — | 9,191 |
| Logic Array Blocks | — | 7,904 |
| Total Package Pins or Balls | — | 1,020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Tension d'alimentation | — | [DATA_NEEDED: operating supply voltage] |
| Speed Grade | — | C5 |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Embedded Memory Capacity | — | [DATA_NEEDED: embedded memory capacity] |
| Phase-Locked Loops | — | [DATA_NEEDED: PLL count] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |