EP1S80F1020C7NGA vs EP1S80F1020C5N Comparaison
Comparaison détaillée côte à côte de EP1S80F1020C7NGA par Altera et EP1S80F1020C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1S80F1020C7NGA - Stratix 79,040 LE FPGA, 773 I/O, 1020-BGA | Altera
EP1S80F1020C7NGA ObsoleteComparaison des spécifications
| Paramètre | EP1S80F1020C7NGA | EP1S80F1020C5N |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Fin de vie |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $198,00 | $0,00 |
| Family | Stratix | — |
| Logic Elements (LEs) | 79,040 | — |
| Total RAM Bits | 7,427,520 | — |
| User I/O Count | 773 | — |
| Boîtier | 1020-BGA (FineLine BGA) | — |
| Process Node | 130 nm | — |
| DSP Blocks | 22 | — |
| Transceivers | 8 channels, up to 3.125 Gbps | — |
| PLLs | 6 | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT] | — |
| Température de fonctionnement | 0C to +85C (commercial) | 0 °C to 85 °C |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | Compliant (Pb-free NGA finish) | unknown |
| Lead-Free Finish | Yes (NGA = Pb-free) | — |
| Configuration Method | JTAG / Passive Serial / Fast Passive Parallel | — |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | Stratix |
| Logic Technology | — | CMOS |
| Logic Elements | — | 79,040 |
| Logic Cells | — | 9,191 |
| Logic Array Blocks | — | 7,904 |
| User I/O Pins | — | 773 I/O |
| Total Package Pins or Balls | — | 1,020 |
| Package Type | — | FBGA-1020 |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1 mm |
| Tension d'alimentation | — | [DATA_NEEDED: operating supply voltage] |
| Speed Grade | — | C5 |
| REACH Status | — | unknown |
| AEC-Q100 Qualification | — | not_applicable |
| Embedded Memory Capacity | — | [DATA_NEEDED: embedded memory capacity] |
| Phase-Locked Loops | — | [DATA_NEEDED: PLL count] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |