EP1SGX25FF1020C6 vs EP1SGX25FF1020C5L Comparaison
Comparaison détaillée côte à côte de EP1SGX25FF1020C6 par Intel et EP1SGX25FF1020C5L par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP1SGX25FF1020C6 - Stratix GX FPGA 25,660 LE 607 I/O FBGA-1020 | Intel
EP1SGX25FF1020C6 Obsolete
Comparaison des spécifications
| Paramètre | EP1SGX25FF1020C6 | EP1SGX25FF1020C5L |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $135,00 | $105,00 |
| Family | Stratix GX | Stratix GX |
| Series | Stratix GX | — |
| Logic Family | CMOS | — |
| Logic Elements / Cells | 25,660 | — |
| Number of LABs | 2,566 | — |
| Total Memory Bits | 1,944,576 (1.94 Mbit, TriMatrix) | — |
| User I/O Count | 607 | — |
| Nombre de broches | 1020 | — |
| Package Type | FBGA-1020 (FC-FBGA) | FC-FBGA (Flip-Chip Fine-pitch Ball Grid Array) |
| Package Dimensions | 33 x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| Core Supply Voltage | 1.5 V | — |
| Température de fonctionnement | 0 °C to 85 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | C6 | C5 (slowest tier) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Non-Compliant (legacy Altera era) | [DATA_NEEDED: RoHS compliance] |
| Lead Free | Yes | — |
| Logic Elements | — | 25,660 cells |
| Process Technology | — | 130 nm CMOS |
| Nombre de broches | — | 1020 balls |
| Core Voltage | — | 1.5 V |
| Maximum Transceiver Data Rate | — | 3.125 Gbps |
| Maximum Operating Frequency | — | 5000 MHz (internal reference) |
| Memory Architecture | — | TriMatrix (M512/M4K/M-RAM blocks) |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, HSTL, SSTL |
| Configuration Scheme | — | Active serial (EPCS), passive serial, JTAG |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |