EP1SGX40FF1020I7 vs EP1SGX40FF1020C7 Comparaison
Comparaison détaillée côte à côte de EP1SGX40FF1020I7 par Intel et EP1SGX40FF1020C7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP1SGX40FF1020I7 | EP1SGX40FF1020C7 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 500,00 | $750,00 |
| Family | Stratix GX | Stratix GX (EP1SGX40) |
| Logic Elements (LEs) | 41,250 | — |
| Embedded Memory (bits) | 3,423,744 | 3,423,744 |
| Embedded Memory (M4K blocks) | 384 | — |
| Embedded Memory (M512 blocks) | 319 | — |
| Embedded Memory (M-RAM blocks) | 9 | — |
| DSP Blocks | 14 (8 9x9 multipliers per block) | — |
| Embedded Transceivers | 48 channels | — |
| Maximum Transceiver Data Rate | 3.1875 Gbps | — |
| Minimum Transceiver Data Rate | 600 Mbps | — |
| PLLs | 12 (8 fast PLLs, 4 enhanced PLLs) | 8 enhanced + per-transceiver PLLs |
| Maximum User I/O Pins | 624 | — |
| Boîtier | 1020-pin FCBGA (FF1020) | 1020-ball FC-FBGA (S-PBGA-B1020) |
| Température de fonctionnement | -40C to +100C (Industrial grade, suffix I) | 0 °C to 85 °C (commercial) |
| Core Voltage | 1.5 V | — |
| Speed Grade | 7 | 7 (-7, mid-speed) |
| Statut RoHS | unknown | Compliant |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Total RAM bits | 3,423,744 | — |
| Series | — | Stratix GX |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Process Technology | — | CMOS |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Type de montage | — | Surface Mount |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |