EP20K1000CF672C8N vs EP20K1000CF672C8 Comparaison
Comparaison détaillée côte à côte de EP20K1000CF672C8N par Intel et EP20K1000CF672C8 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K1000CF672C8N | EP20K1000CF672C8 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $178,40 | $245,09 |
| Device Family | APEX 20KC | — |
| Device Type | FPGA (Field Programmable Gate Array) | Field Programmable Gate Array (FPGA) |
| Logic Elements / Cells | 38,400 | 38,400 |
| Equivalent Gate Count | 1,000,000 gates | — |
| Embedded Memory (bits) | 327,680 | — |
| Number of I/Os | 488 to 508 | — |
| Number of Pins / Balls | 672 | — |
| Boîtier | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | 0°C to 85°C (Commercial) | 0C to 85C (commercial) |
| Supply Voltage (Vccint) | 1.8 V | — |
| Process Technology | 0.15 µm all-layer copper | 0.15 um all-layer copper CMOS |
| Internal Operating Frequency (max) | 301.21 MHz | — |
| Propagation Delay (typ.) | 1.6 ns to 1.79 ns | — |
| Architecture | MultiCore (LUT + embedded memory + product-term) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | unknown (legacy part, verify on lot) |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| Pin-to-Pin Compatibility | APEX 20KE family (same 672-ball BGA) | — |
| Series | — | APEX 20KC |
| System Gates | — | 1,000,000 |
| Embedded RAM | — | 327,680 bits |
| User I/Os | — | 488 (datasheet), 508 (per some distributor listings) |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Number of Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Number of PLLs | — | 4 |
| Maximum User I/O Pins | — | 488 |
| Core Voltage (VCCINT) | — | 1.8 V (typical) |
| I/O Voltage (VCCIO) | — | Multi-voltage (LVTTL/LVCMOS/LVDS/SSTL/GTL+ compatible) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Mode | — | FPP / Passive Serial / JTAG |