EP20K100EBC652-2X vs EP20K1000EBC652-2X Comparaison
Comparaison détaillée côte à côte de EP20K100EBC652-2X par Altera et EP20K1000EBC652-2X par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X NrndComparaison des spécifications
| Paramètre | EP20K100EBC652-2X | EP20K1000EBC652-2X |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $85,00 | $99,00 |
| Family | APEX 20KE | APEX-20KE |
| Typical Gates | 100,000 | 1,000,000 system gates |
| Maximum System Gates | 263,000 | — |
| Logic Elements | 4,160 | — |
| Embedded System Blocks (ESBs) | 26 | — |
| Maximum RAM Bits | 53,248 | — |
| Maximum User I/O Pins | 246 | — |
| Supply Voltage - Core | 1.8 V | — |
| Supply Voltage - I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Boîtier | 652-ball BGA (EBC652) | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) |
| Speed Grade | -2 (faster commercial) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS |
| Température de fonctionnement | 0C to +85C (commercial) | 0 °C to +85 °C (commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Method | Passive Serial / Passive Parallel / JTAG (EPC) | — |
| Clock Resources | Up to 4 DLLs, multiple global clocks | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Device Logic Elements | — | 38,400 |
| Embedded Memory Bits | — | 327,680 bits |
| User I/O Pins | — | 488 |
| Maximum User I/O | — | 488 |
| Propagation Delay | — | 1.6 ns |
| Internal Maximum Frequency | — | 350 MHz |
| Logic Blocks / Macros | — | 2,560 macros |
| PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Altera configuration |