EP20K1500CF33C7ES vs EP20K1500CF33C8ES Comparaison
Comparaison détaillée côte à côte de EP20K1500CF33C7ES par Intel et EP20K1500CF33C8ES par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K1500CF33C7ES | EP20K1500CF33C8ES |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $138,00 | $288,00 |
| Family | APEX20K | — |
| Series | APEX 20K | APEX 20K (APEX 20KE family) |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Logic Elements / Cells | 51840 | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | — |
| Number of I/O | 808 | — |
| Number of Gates | 1500000 | — |
| Voltage - Supply | 2.5V core, 3.3V I/O | — |
| Température de fonctionnement | 0C to +85C (commercial) | [DATA_NEEDED: operating temperature range] |
| Type de montage | Surface Mount | Surface Mount |
| Boîtier / Format | 1020-BBGA, FCBGA (FineLine BGA) | — |
| Supplier Device Package | 1020-BGA | — |
| Programmable Type | In System Programmable (SRAM-based) | — |
| Configuration Method | SRAM / JTAG | — |
| I/O Standards | LVTTL, LVCMOS, PCI, GTL, SSTL | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance for ES variant] |
| System Gates | — | 1,500,000 |
| Maximum Gates (Equivalent) | — | 2,392,000 |
| Logic Elements | — | 51,840 |
| Embedded System Block (ESB) Bits | — | 442,368 |
| CAM Bits | — | 216 Kbit |
| Number of PLLs | — | 4 |
| Number of Clocks | — | 8 clock pins |
| Maximum User I/O | — | 808 (1020-FBGA) |
| Boîtier | — | 1020-FBGA (FCBGA), 33x33 mm |
| Speed Grade | — | -1 (C8) |
| Voltage - Supply (Core) | — | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Interface | — | ByteBlaster / MasterBlaster / Altera USB-Blaster |
| Sample Tier | — | ES (engineering sample) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |