EP20K160EQC240-2 vs EP20K160EQC240-2X Comparaison
Comparaison détaillée côte à côte de EP20K160EQC240-2 par Intel et EP20K160EQC240-2X par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K160EQC240-2 | EP20K160EQC240-2X |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $108,50 | $22,75 |
| Family | APEX 20KE | — |
| Typical Gates | 160,000 | — |
| Logic Elements (LEs) | 6,400 | — |
| Embedded System Blocks (ESBs) | 64 | — |
| Maximum Embedded Memory | 56 Kbits (approx. 7 Kbytes usable) | — |
| Maximum User I/O (this package) | 175 | — |
| Maximum User I/O (largest package) | 271 | — |
| PLLs | 4 | — |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.55 ns | — |
| Logic Family | CMOS | CMOS |
| Process Technology | 0.18-micron SRAM CMOS | — |
| Boîtier | PQFP-240 (QFP-240, FQFP) | 240-BQFP (PQFP-240, 32x32 mm) |
| Nombre de broches | 240 | — |
| Type de montage | Surface Mount (Gull Wing) | Surface Mount (PQFP, gull-wing leads) |
| Température de fonctionnement | 0 C to 85 C (Commercial) | 0 C to 85 C (Commercial) |
| Speed Grade | -2 | -2 |
| Supply Voltage (core) | [DATA_NEEDED: core VCC value] | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS | — |
| Configuration Modes | Passive Serial, Passive Parallel Synchronous, JTAG | — |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | — |
| Statut RoHS | Non-compliant (original Altera-era PQFP) | [DATA_NEEDED: lead-free / RoHS status] |
| MultiCore Architecture | Yes (Logic + ESB + I/O) | — |
| 5.0 V Tolerance | Achievable with external resistor | — |
| Series | — | APEX-20KE |
| Logic Elements | — | 6,400 |
| System Gates | — | 160,000 |
| Embedded Memory Bits | — | 345,600 |
| Maximum Internal Frequency | — | 350 MHz |
| Propagation Delay (Tpd) | — | 1.93 ns |
| Number of I/Os | — | 175 (Mouser) / 271 (datasheet summary) |
| Number of PLLs | — | 4 |
| Core Process Technology | — | 0.22 um CMOS |
| Core Voltage | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V compatible) |
| Programming Interface | — | IEEE 1149.1 JTAG + Altera ByteBlaster |