EP20K160EQC240-3N vs EP20K160EQC240-2 Comparaison
Comparaison détaillée côte à côte de EP20K160EQC240-3N par Intel et EP20K160EQC240-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K160EQC240-3N | EP20K160EQC240-2 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,50 | $108,50 |
| Family | APEX 20K | APEX 20KE |
| Logic Family | CMOS | CMOS |
| System Gates | 160,000 | — |
| Logic Elements / Cells | 6400 | — |
| Embedded Memory | 87,040 bits (EAB) | — |
| User I/Os | 271 | — |
| Internal Frequency | 323 MHz | — |
| Propagation Delay | 1.55 ns | 1.55 ns |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 3.3 V | — |
| Process Technology | 0.22 µm CMOS | 0.18-micron SRAM CMOS |
| Température de fonctionnement | 0 °C to 85 °C | 0 C to 85 C (Commercial) |
| Boîtier | 240-pin PQFP (Power Quad Flat Pack) | PQFP-240 (QFP-240, FQFP) |
| Speed Grade | -3 | -2 |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (original Altera-era PQFP) |
| Programmability | In-system via JTAG (IEEE 1149.1) | — |
| Typical Gates | — | 160,000 |
| Logic Elements (LEs) | — | 6,400 |
| Embedded System Blocks (ESBs) | — | 64 |
| Maximum Embedded Memory | — | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | — | 175 |
| Maximum User I/O (largest package) | — | 271 |
| PLLs | — | 4 |
| Internal Frequency (max) | — | 160 MHz |
| Nombre de broches | — | 240 |
| Type de montage | — | Surface Mount (Gull Wing) |
| Supply Voltage (core) | — | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |
| MultiCore Architecture | — | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | — | Achievable with external resistor |