EP20K200EBC652-3N vs EP20K200CB652C7ES Comparaison
Comparaison détaillée côte à côte de EP20K200EBC652-3N par Altera et EP20K200CB652C7ES par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K200CB652C7ES - APEX 20K 200K FPGA 652-BGA | Altera/Intel
EP20K200CB652C7ES ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K200EBC652-3N | EP20K200CB652C7ES |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $220,00 | $275,00 |
| Series | APEX 20KE (APEX-20KE®) | — |
| Device Family | EP20K200 | — |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | — |
| Logic Array Blocks (LABs) | 832 | — |
| Macrocells | 832 | — |
| Embedded RAM | 106,496 bits | — |
| User I/Os (DigiKey listing) | 376 | — |
| User I/Os (digchip listing) | 277 | — |
| Propagation Delay | 2.33 ns | — |
| Internal Frequency (max) | 189 MHz | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 1.71 V to 1.89 V (nominal 1.8 V) | — |
| I/O Supply (LVDS-capable) | LVDS, 2.5 V referenced (per source variant) | — |
| Boîtier | 652-ball BGA | 652-BGA |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature (TJ) | 0 °C to 85 °C (commercial) | — |
| Speed Grade | -3 (slowest in APEX 20KE family) | -7 |
| Configuration | JTAG (IEEE 1149.1), Passive Serial | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Family | — | APEX 20K |
| Logic Elements | — | 8,320 |
| Embedded System Block (ESB) RAM | — | 106,496 bits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count for 652-BGA] |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Operating Temperature (Commercial) | — | 0 °C to +85 °C |
| Configuration Method | — | SRAM (volatile, requires external PROM on power-up) |
| PLL Count | — | Up to 8 |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+, SSTL, LVDS |
| JTAG (IEEE 1149.1) | — | Yes (boundary-scan) |
| Configuration Device Compatibility | — | EPC2, EPC8, EPC16, EPC64, microprocessor |
| Niveau MSL | — | [DATA_NEEDED: moisture sensitivity level] |