EP20K200EQC240-1 vs EP20K160EQC240-2 Comparaison
Comparaison détaillée côte à côte de EP20K200EQC240-1 par Intel et EP20K160EQC240-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K200EQC240-1 | EP20K160EQC240-2 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $108,50 |
| Product Type | FPGA (Field Programmable Gate Array) | — |
| FPGA Family | APEX 20KE | — |
| Logic Elements | 8,320 | — |
| Total RAM Bits | 106,496 | — |
| Maximum User I/O | 168 | — |
| Number of Terminals | 240 | — |
| Boîtier | 240-BFQFP (S-PQFP-G240) | PQFP-240 (QFP-240, FQFP) |
| Package Body Size | 32 mm x 32 mm | — |
| Terminal Pitch | 0.5 mm | — |
| Terminal Form | Gull wing | — |
| Package Shape | Square | — |
| Speed Grade | -1 | -2 |
| Logic Family | CMOS | CMOS |
| Propagation Delay | 2.5 ns | 1.55 ns |
| Type de montage | Surface Mount | Surface Mount (Gull Wing) |
| Core Supply Voltage | [DATA_NEEDED: core supply voltage] | — |
| I/O Supply Voltage | [DATA_NEEDED: I/O supply voltage] | — |
| Température de fonctionnement | [DATA_NEEDED: temperature grade] | 0 C to 85 C (Commercial) |
| Family | — | APEX 20KE |
| Typical Gates | — | 160,000 |
| Logic Elements (LEs) | — | 6,400 |
| Embedded System Blocks (ESBs) | — | 64 |
| Maximum Embedded Memory | — | 56 Kbits (approx. 7 Kbytes usable) |
| Maximum User I/O (this package) | — | 175 |
| Maximum User I/O (largest package) | — | 271 |
| PLLs | — | 4 |
| Internal Frequency (max) | — | 160 MHz |
| Process Technology | — | 0.18-micron SRAM CMOS |
| Nombre de broches | — | 240 |
| Supply Voltage (core) | — | [DATA_NEEDED: core VCC value] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, GTL+, LVDS |
| Configuration Modes | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |
| Statut RoHS | — | Non-compliant (original Altera-era PQFP) |
| MultiCore Architecture | — | Yes (Logic + ESB + I/O) |
| 5.0 V Tolerance | — | Achievable with external resistor |