EP20K400CB652C9 vs EP20K400CF672C-8 Comparaison
Comparaison détaillée côte à côte de EP20K400CB652C9 par Intel et EP20K400CF672C-8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400CB652C9 | EP20K400CF672C-8 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $89,20 | $95,00 |
| Family | APEX 20KC | APEX 20K |
| Logic Elements | 16640 | 16,640 |
| Gate Count | 400000 | — |
| Maximum Operating Frequency | 250 MHz | — |
| User I/Os | 488 | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage | 1.8 V | — |
| Propagation Delay | 2.5 ns | — |
| Température de fonctionnement | 0 °C to +85 °C (Commercial) | — |
| Boîtier | BGA-652, 45 × 45 mm, 1.27 mm pitch | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Number of PLLs | 4 | — |
| Embedded Memory Blocks | MultiCore ESBs (Embedded System Blocks) | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, HSTL, SSTL (MultiVolt I/O) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Typical Gates | — | 400,000 |
| Macros | — | 1,664 |
| Maximum User I/O | — | 488 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Package Type | — | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) |
| Core Voltage (VCCINT) | — | 1.8 V nominal (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO options] |
| Pin-to-Pin Delay (tPD) | — | 1.78 ns (speed grade -8) |
| Speed Grade | — | -8 |
| Temperature Grade (C) | — | Commercial, 0 °C to 85 °C |
| Embedded Memory Type | — | ESB (RAM / ROM / CAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |