EP20K400GC655-2V vs EP20K400GC655-1 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2V par Altera et EP20K400GC655-1 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Dernier achatIntel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteComparaison des spécifications
| Paramètre | EP20K400GC655-2V | EP20K400GC655-1 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,75 | $135,00 |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | 16,640 |
| Total RAM Bits | 212,992 | 212,992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | 2.5 ns |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | — |
| Boîtier | 655-CPGA (62.48 x 62.48 mm) | 655-pin CPGA (Ceramic Pin Grid Array) |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Type de montage | Through-hole (CPGA) | Through-Hole |
| Speed Grade | -2 | — |
| Température de fonctionnement | [DATA_NEEDED: temperature grade] | 0 °C to +85 °C (commercial) |
| Statut RoHS | unknown | Non-compliant (contains lead in ceramic package) |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Nombre de broches | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |