EP20K400GC655-2V vs EP20K400GC655-2N Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-2V par Altera et EP20K400GC655-2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K400GC655-2V | EP20K400GC655-2N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $92,75 | $127,50 |
| Series | APEX-20KC | — |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20KC |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | 1.71 V to 1.89 V |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | Yes |
| Boîtier | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Type de montage | Through-hole (CPGA) | Through-Hole (CPGA, socket-compatible) |
| Speed Grade | -2 | — |
| Température de fonctionnement | [DATA_NEEDED: temperature grade] | Industrial (per Altera part-number -N suffix) |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | MultiCore (LUT + product-term + embedded memory) |
| Number of Logic Elements | — | 16640 |
| Number of Logic Cells | — | 16640 |
| Total System Gates | — | 400000 |
| Number of LABs/CLBs | — | [DATA_NEEDED: LAB count] |
| I/O Voltage (VCCIO) | — | 2.5 V (LVDS-capable) |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay (Tpd) | — | 3.1 ns |
| Boîtier / Format | — | 655-BCPGA (Ceramic Pin Grid Array) |
| Supplier Device Package | — | 655-CPGA, 62.48 x 62.48 mm |
| Configuration Method | — | JTAG / Passive Serial |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |