EP20K400GC655-3V vs EP20K400GI655-1V Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-3V par Intel et EP20K400GI655-1V par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K400GC655-3V | EP20K400GI655-1V |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $160,00 | $155,00 |
| Series | APEX-20KC | — |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) | APEX 20K |
| Manufacturer | Altera (now Intel) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 2.5 V |
| Logic Elements | 16640 | 16,640 |
| Total RAM Bits | 212992 | — |
| Typical Gate Count | 400000 | — |
| Number of User I/O | 496 | — |
| Fréquence d'horloge maximale | 714.2 MHz | — |
| Propagation Delay | 3.6 ns | 2.5 ns |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) | — |
| Boîtier | 655-BCPGA (62.48 mm x 62.48 mm) | — |
| Package Equivalence Code | SPGA655, 47x47 | SPGA655, 47x47 |
| Type de montage | Through Hole (CPGA) | — |
| Peak Reflow Temperature | 220 C | — |
| Process Technology | CMOS | CMOS |
| Configuration | SRAM-based (requires EPC configuration device) | In-system programmable via JTAG |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] | [DATA_NEEDED] |
| Température de fonctionnement | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: industrial vs military grade] |
| Typical Gates | — | 400,000 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 4 |
| Package Type | — | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Boundary Scan | — | IEEE 1149.1 JTAG |
| Niveau MSL | — | 1 |
| Package Body Material | — | Ceramic |