EP20K600CB652C9 vs EP20K600CB652C7ES Comparaison
Comparaison détaillée côte à côte de EP20K600CB652C9 par Altera et EP20K600CB652C7ES par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CB652C9 | EP20K600CB652C7ES |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $142,50 | $195,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 24,320 | — |
| Number of LABs / CLBs | 2,432 | — |
| System Gates | 1,537,000 | 600,000 |
| Total RAM Bits | 311,296 | — |
| User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Tension d'alimentation | 1.71 V to 1.89 V | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm CMOS |
| Internal Datapath Frequency | up to 250 MHz | — |
| Propagation Delay (typ.) | 1.48 ns | — |
| Température de fonctionnement | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Boîtier | 652-BGA (45 × 45 mm, 1.27 mm pitch) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Configuration | JTAG IEEE 1149.1 / serial / EPC2-compatible | — |
| Statut RoHS | Compliant (per Altera product page) | [DATA_NEEDED: RoHS status] |
| Product Status | Obsolete (per distributor listings) | — |
| Logic Elements | — | 24,320 |
| Maximum System Gates | — | 1,053,840 |
| Embedded Memory Bits | — | 311,296 |
| Embedded System Blocks (ESB) | — | 26 |
| Maximum User I/O | — | 488 |
| User I/O (this package) | — | 488 (652-BGA) |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Internal Clock Frequency | — | 1666.6 MHz |
| Propagation Delay | — | 1.6 ns |
| Package Type | — | 652-ball FineLine BGA |
| JEDEC Package Code | — | S-PBGA-B652 |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| PLLs | — | 4 |