EP20K600CB652I7N vs EP20K600CB652I8 Comparaison
Comparaison détaillée côte à côte de EP20K600CB652I7N par Altera et EP20K600CB652I8 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CB652I7N | EP20K600CB652I8 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $158,00 | $92,00 |
| Family | APEX 20KC | APEX 20KC |
| Typical Gates | 600,000 | — |
| Logic Elements (Cells) | 24,320 | — |
| Maximum Operating Frequency | 375.94 MHz | 301.21 MHz |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Supply Voltage (VCCINT) | 1.8 V | 1.8 V nominal (1.71 V to 1.89 V) |
| Boîtier | 652-pin FineLine BGA | 652-ball FineLine BGA (S-PBGA-B652) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| User I/O Banks | [DATA_NEEDED: User I/O Banks] | — |
| Maximum User I/O | [DATA_NEEDED: Maximum User I/O] | — |
| Embedded System Block (ESB) Memory | 311,040 bits | — |
| Phase-Locked Loops (PLLs) | 4 | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Speed Grade | 7 | — |
| Configuration Method | SRAM-based, JTAG (IEEE 1149.1) | — |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | EP20K600 |
| System Gates | — | 600,000 |
| Logic Elements / Cells | — | 24,320 |
| Propagation Delay (tpd) | — | 1.78 ns (CMOS) |
| Température de fonctionnement | — | -40 °C to +85 °C (Industrial) |
| Package Code | — | BGA, square |
| Ball Pitch | — | 1.27 mm |
| Package Body Size | — | 45 mm × 45 mm |
| User I/O Lines | — | 488 |
| Dedicated Clock Inputs | — | 4 |
| Programming Interface | — | IEEE 1149.1 JTAG (in-system) |