EP20K600CB672C8 vs EP20K600CB652C9N Comparaison
Comparaison détaillée côte à côte de EP20K600CB672C8 par Intel et EP20K600CB652C9N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP20K600CB672C8 - APEX 20KC FPGA 600K Gates 672-FBGA | Intel / Altera
EP20K600CB672C8 Obsolete
Comparaison des spécifications
| Paramètre | EP20K600CB672C8 | EP20K600CB652C9N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $245,00 | $128,00 |
| Series | APEX 20KC | — |
| Family | APEX-20KC® | APEX 20KC |
| Number of Logic Elements/Cells | 24320 | — |
| Total RAM Bits | 311296 | — |
| Number of I/O | 508 | — |
| Number of Gates | 600000 | — |
| Voltage - Supply | 1.71 V to 1.89 V (core); 3.0 V to 3.6 V (I/O) | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | 0 °C to +85 °C (commercial) | 0 C to 85 C (commercial) |
| Boîtier / Format | 672-BBGA, FCBGA (27 x 27 mm) | — |
| Supplier Device Package | 672-FBGA (27 x 27) | — |
| Speed Grade | C8 (approx. 301 MHz internal) | C9 (~1.48 ns propagation delay) |
| Process Technology | 0.15 µm CMOS | 0.15 micron all-layer copper CMOS |
| PLLs | 4 | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, GTL+, PCI 3.3 V | — |
| Statut RoHS | Unknown (legacy part, pre-RoHS era) | [DATA_NEEDED: rohs status] |
| Lead Free | Unknown | — |
| Device Type | — | Loadable PLD (FPGA) |
| Typical Gates | — | 600,000 |
| Logic Elements | — | 24,320 |
| Maximum User I/O | — | 488 |
| Boîtier | — | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.8 V |
| Architecture | — | MultiCore LUT + embedded system memory (ESB) |
| On-chip Memory | — | Embedded system memory blocks (dual-port RAM, FIFO) |
| Configuration Interface | — | JTAG (IEEE 1149.1) and serial/PROM configuration |
| Pin/Pin Compatibility | — | Pin-compatible with APEX 20KE devices of same package |
| Toolchain | — | Altera/Intel Quartus II (legacy APEX support) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |