EP20K600CF672I9 vs EP20K600CF672I7 Comparaison
Comparaison détaillée côte à côte de EP20K600CF672I9 par Intel et EP20K600CF672I7 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672I9 | EP20K600CF672I7 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $152,00 | $220,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements / Cells | 24,320 | — |
| System Gates | 600,000 | 600,000 |
| Maximum Operating Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.8 V | — |
| Boîtier | 672-pin FC-FBGA | 672-ball FineLine BGA (FC-FBGA, 27×27 mm) |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Temperature Grade | Industrial (-40°C to +85°C) | — |
| Speed Grade | 9 (fastest bin) | -7 |
| User I/O Pins | 311 (max) | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded Memory | [DATA_NEEDED: total RAM bits] | — |
| PLLs | Up to 4 | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, LVDS | — |
| Configuration Mode | Passive Serial / JTAG | — |
| Maximum Seated Height | 2.1 mm | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Maximum Logic Elements | — | 24,320 cells |
| Maximum User I/O | — | 508 |
| Maximum Internal Frequency | — | 375.94 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V (LVTTL/LVCMOS compatible) |
| Température de fonctionnement | — | -40 °C to +100 °C (industrial, I-suffix) |
| Ball Pitch | — | 1.00 mm |
| Embedded System Blocks | — | Yes (dual-port RAM / CAM) |
| Configuration Interface | — | IEEE 1149.1 JTAG, passive serial, fast passive parallel |