EP20K60EFC324-3N vs EP20K60EFC324-3 Comparaison
Comparaison détaillée côte à côte de EP20K60EFC324-3N par Altera et EP20K60EFC324-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K60EFC324-3N | EP20K60EFC324-3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $35,40 | $58,40 |
| Series | APEX-20KE | APEX 20KE |
| Number of Logic Elements | 2560 Cells | — |
| Total Gates | 60K Gates (60000 typical) | 60000 |
| Number of User I/Os | 196 | — |
| Boîtier / Format | 324-BGA / 324-FBGA (19x19) | 324-FBGA (19x19 mm, 1.0 mm pitch) |
| Supplier Device Package | 324-FBGA (19x19) | — |
| Core Supply Voltage | 1.71V ~ 1.89V (1.8V nominal) | — |
| Température de fonctionnement | 0°C ~ 85°C (TJ) | 0°C to +85°C (commercial) |
| Maximum Internal Frequency | 182 MHz (-3 speed grade) | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Nombre de broches | 324 | — |
| Type de montage | Surface Mount | Surface Mount |
| Total RAM Bits | [DATA_NEEDED: total RAM bits per APEX 20K datasheet] | — |
| Embedded System Blocks | [DATA_NEEDED: ESB count] | — |
| I/O Standards Supported | [DATA_NEEDED: I/O standards list] | — |
| Statut RoHS | [DATA_NEEDED: explicit RoHS statement] | unknown |
| Packaging | Bulk (per distributor listing) | — |
| Ordering Suffix | -N suffix ordering variant | — |
| Family | — | APEX 20K |
| Logic Elements / Cells | — | 2560 |
| User I/Os | — | 196 |
| Number of Logic Blocks / LABs | — | 256 |
| Embedded Memory (EAB/ESB) Bits | — | 24576 |
| Internal Frequency (max) | — | 160 MHz |
| Propagation Delay | — | 1.72 ns |
| Peak Performance Frequency | — | 182 MHz |
| Core Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | 3.3 V (3.0 V to 3.6 V) |
| Logic Family | — | CMOS |
| Programmable Type | — | In-system programmable (SRAM) |
| Configuration Interface | — | JTAG (IEEE 1149.1) + passive serial |