EP2A40F1020C7ES vs EP2A40B724C7 Comparaison
Comparaison détaillée côte à côte de EP2A40F1020C7ES par Intel et EP2A40B724C7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A40F1020C7ES | EP2A40B724C7 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $185,00 | $650,00 |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | — |
| Typical Gates | 1,500,000 | — |
| Embedded Memory | 655,360 bits | — |
| Maximum User I/O | 735 | 540 |
| Maximum Frequency | 562 MHz | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm CMOS, up to 8 metal layers, all-layer copper |
| Core Voltage | 1.5 V | — |
| Boîtier | 1020-pin FC-FBGA | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm |
| Speed Grade | C7 (with ES enhanced speed suffix) | — |
| High-Speed Interface | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial grade] | 0 °C to +85 °C (commercial) |
| I/O Standards | LVTTL, LVCMOS, LVDS, LVPECL, PCML, HyperTransport, 1.5/1.8/2.5/3.3 V | — |
| PLLs | Up to 8 (per datasheet family feature) | 4 |
| Statut RoHS | [DATA_NEEDED] | Non-compliant (lead-bearing FCBGA) |
| Programming Interface | JTAG (IEEE 1149.1), passive serial | — |
| Type de montage | Surface Mount (FC-FBGA) | Surface Mount (BGA) |
| Logic Elements / Cells | — | 38,400 |
| Total System Gates | — | 1,500,000 |
| Embedded RAM Bits | — | 655,360 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (typ. 1.5 V) |
| Maximum Internal Frequency | — | 562 MHz |
| I/O Standards Supported | — | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices |
| MultiVolt I/O Support | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| DDR Memory Support | — | Yes (via ESB / I/O circuitry) |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |