EP2A40F1020C8N vs EP2A40F1020C7N Comparaison
Comparaison détaillée côte à côte de EP2A40F1020C8N par Intel et EP2A40F1020C7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP2A40F1020C7N - APEX II 1.5M Gates FPGA, 735 I/O, FC-FBGA-1020 | Intel
EP2A40F1020C7N ObsoleteComparaison des spécifications
| Paramètre | EP2A40F1020C8N | EP2A40F1020C7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $198,00 |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | — |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | — |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Température de fonctionnement | 0 °C to 85 °C | 0 °C to +85 °C (commercial, C7 grade) |
| Type de montage | Surface Mount | Surface Mount |
| Terminal Form | Ball | BGA ball (flip-chip) |
| Statut RoHS | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| Technology | — | 0.15 µm all-layer copper CMOS, up to 8 metal layers |
| System Gates | — | 1,500,000 (1.5 M) |
| Logic Elements | — | 38,400 |
| Embedded Memory | — | ESB-based, 504 Kbits total |
| Maximum Internal Performance | — | 562 MHz |
| Propagation Delay | — | 1.55 ns |
| User I/O Pins | — | 735 |
| PLLs | — | 4 |
| Clock Networks | — | 12 |
| True-LVDS Data Rate | — | 1 Gbps |
| Supported I/O Standards | — | True-LVDS, LVPECL, PCML, HyperTransport, LVTTL, LVCMOS, PCI, SSTL |
| Core Supply Voltage | — | 1.5 V nominal (1.425 V – 1.575 V) |
| Logic Family | — | CMOS |
| Boîtier | — | FC-FBGA-1020, 33 × 33 mm, 1.0 mm pitch, fine-line |