EP2A70F1020C9 vs EP2A70F1020 Comparaison
Comparaison détaillée côte à côte de EP2A70F1020C9 par Intel et EP2A70F1020 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A70F1020C9 | EP2A70F1020 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $132,80 | $118,50 |
| Family | APEX II (APII) | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Typical Gates | ~70,000 gates | — |
| Boîtier | 1020-ball FBGA (FineLine BGA) | 1020-ball FBGA (FineLine BGA) |
| User I/O Pins | 735 | 735 |
| Speed Grade | -9 (fastest) | — |
| Operating Temperature Grade | Commercial (C) | — |
| Configuration Method | JTAG / passive serial / passive parallel | — |
| Core Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal value] | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO nominal value] | — |
| On-chip Memory | EABs (Embedded Array Blocks) | — |
| Embedded Multipliers | Yes (DSP blocks in LABs) | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | 3 (JEDEC J-STD-020) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements / Cells | — | 67200 |
| Core Voltage | — | 1.5 V |
| Configuration Interface | — | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) |
| SRAM-based Configuration | — | Yes (volatile - requires external configuration memory) |
| Température de fonctionnement | — | -40C to +85C (commercial/industrial) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, LVDS, SSTL, GTL+ (per APEX II family spec) |
| Embedded System Blocks (ESB) | — | Yes (RAM and arithmetic functions) |
| Process Technology | — | [DATA_NEEDED: process node] |
| Embedded Multipliers / DSP Blocks | — | Not in original APEX II (no hard DSP blocks; implemented in ESB logic) |
| Part Status / Lifecycle | — | Obsolete - superseded by Altera Stratix and Cyclone families |