EP2A70F1508I-8 vs EP2A70F1508C8 Comparaison
Comparaison détaillée côte à côte de EP2A70F1508I-8 par Altera et EP2A70F1508C8 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A70F1508I-8 | EP2A70F1508C8 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $199,75 | $1 495,00 |
| Series | APEX II (EP2A) | APEX II (EP2A70) |
| Logic Elements | 70,000 (approx.) | 67,200 |
| Boîtier | 1508-ball FineLine BGA (FBGA-1508) | 1508-BBGA, FCBGA (40 x 40 mm) |
| Température de fonctionnement | -40C to +100C (Industrial) | 0 °C to 85 °C (commercial) |
| Speed Grade | -8 | — |
| Configuration Memory | SRAM-based | — |
| Configuration Modes | PS, PPS, PPA, JTAG | — |
| I/O Standards Supported | LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI | — |
| Embedded System Blocks (ESBs) | Yes (RAM/ROM/CAM) | — |
| On-chip PLLs | Yes | — |
| Tension d'alimentation | 1.8 V core (typical APEX II) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Niveau MSL | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-free | [DATA_NEEDED: lead-free status] | — |
| MultiCore Interconnect | Yes | — |
| Design Software | Quartus II (APEX II support up to v13.0) | — |
| Device Family | — | APEX II |
| Embedded RAM Bits | — | 1,146,880 |
| User I/O Count | — | 1060 |
| Maximum User I/O Pins | — | 1060 |
| Process Technology | — | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | — | 1.425 V to 1.575 V (1.5 V nominal) |
| High-Speed Interface Support | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| Type de mémoire | — | Embedded dual-port RAM / ROM via ESBs |
| Architecture | — | Embedded array with LABs + ESBs |