EP2AGX125EF35C6G vs EP2AGX95EF35C6 Comparaison
Comparaison détaillée côte à côte de EP2AGX125EF35C6G par Altera et EP2AGX95EF35C6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2AGX125EF35C6G | EP2AGX95EF35C6 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $398,00 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Series | Arria II GX | — |
| Number of Logic Elements/Cells | 118143 | — |
| Total RAM Bits | 8315904 bit | — |
| User I/O Pins | 452 | — |
| Core Supply Voltage | 0.87 V to 0.93 V | — |
| Number of LABs | [DATA_NEEDED: number of LABs] | — |
| Température de fonctionnement | 0 °C to 85 °C (Tj) | — |
| Package Type | 1152-BBGA, FCBGA | — |
| Supplier Device Package | 1152-FBGA (35 mm x 35 mm) | — |
| Package Pin Count | 1152 pin | — |
| Type de montage | [DATA_NEEDED: mounting type] | Surface Mount (FCBGA) |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Device Family | — | Arria II GX |
| Logic Elements (LEs) | — | 89,178 |
| Maximum User I/O Pins | — | 452 |
| Embedded Memory (Kbits) | — | 4,478 |
| Embedded 18x18 Multipliers | — | 612 |
| Number of Transceivers | — | 8 |
| Maximum Transceiver Data Rate | — | 3.75 Gbps |
| Boîtier | — | 1152-ball FCBGA |
| Speed Grade | — | -6 (mid) |
| Process Node | — | 40 nm |
| PCIe Hard IP | — | PCIe Gen1/Gen2 (x1/x4/x8) - per family datasheet |
| Plage de température de fonctionnement | — | Commercial (0C to 85C) per 'C' suffix |
| Configuration Modes | — | Active Serial, Passive Serial, Fast Passive Parallel, JTAG |