EP2AGZ225FF35C4G vs EP2AGX95EF35C4G Comparaison
Comparaison détaillée côte à côte de EP2AGZ225FF35C4G par Intel et EP2AGX95EF35C4G par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2AGZ225FF35C4G | EP2AGX95EF35C4G |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $1 555,00 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Manufacturer | Intel | — |
| Product Family | FPGA | — |
| User I/O | 554 I/O | — |
| Boîtier | 1152FBGA | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Package Type | Fine-pitch ball grid array | — |
| Logic Elements | [DATA_NEEDED: logic element count] | — |
| Embedded Memory | [DATA_NEEDED: embedded memory capacity] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceivers | [DATA_NEEDED: transceiver count] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +85C (commercial) |
| Tension d'alimentation | [DATA_NEEDED: supply voltage] | — |
| I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| Statut RoHS | unknown | Compliant |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Family | — | Arria II GX |
| Logic Elements (LE) | — | 89,178 |
| Adaptive Logic Modules (ALM) | — | [DATA_NEEDED: ALM count from datasheet] |
| Embedded Memory Bits | — | 6,839,296 bits (~6.5 Mbit) |
| Embedded Memory Blocks (M9K/M144K) | — | [DATA_NEEDED: block count from datasheet] |
| Embedded 18x18 Multipliers | — | 616 |
| User I/Os | — | 452 |
| Transceiver Blocks | — | 4 (up to 3.75 Gbps) |
| PCIe Hard IP | — | Gen1/Gen2 (x1/x2/x4) |
| PLLs | — | 4 |
| Global Clock Networks | — | [DATA_NEEDED: per Arria II family datasheet] |
| Process Technology | — | 40 nm TSMC low-power |
| Speed Grade | — | -4 (mid-speed) |
| Configuration Mode | — | Passive Serial, Fast Passive Parallel, JTAG |
| Core Voltage | — | 0.9 V nominal |