EP2AGZ350FF35C3G vs EP2AGZ350FF35I3 Comparaison
Comparaison détaillée côte à côte de EP2AGZ350FF35C3G par Altera et EP2AGZ350FF35I3 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2AGZ350FF35C3G | EP2AGZ350FF35I3 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 680,00 | $4 409,18 |
| Family | Arria II GZ | — |
| Logic Elements (LE) | 350,000 | 348,500 |
| Embedded Memory | 16,860 Kbits | — |
| DSP Blocks (18x18 Multipliers) | 224 | — |
| Transceivers | 8 | Up to 16 channels |
| Transceiver Data Rate | up to 6.375 Gbps | 6.375 Gbps |
| User I/O Pins | 554 | — |
| PLLs | 8 | — |
| Hard Memory Controllers | 2 | — |
| Memory Interface Support | DDR3, DDR2, QDR II+, RLDRAM II | — |
| Maximum Memory Clock | 800 MHz | — |
| Process Node | 40 nm TSMC | 40 nm |
| Boîtier | 1152-FBGA (35 mm x 35 mm, 1.0 mm pitch) | 1152-ball FCBGA (FF35) |
| Température de fonctionnement | 0C to +85C (commercial) | — |
| Core Voltage | 0.9 V | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG, AS | — |
| Statut RoHS | Compliant | Compliant per distributor listings |
| Type de montage | Surface Mount (BGA) | — |
| Series | — | Arria II GZ |
| Embedded Memory Bits | — | 21,270,528 bits |
| Embedded Memory (M9K/M144K) | — | [DATA_NEEDED: block count and distribution] |
| Maximum User I/O | — | 554 |
| DSP Blocks (18x19 multipliers) | — | [DATA_NEEDED: exact multiplier count, datasheet lists up to ~1,368] |
| Ball Pitch | — | 1.0 mm |
| Operating Temperature Grade | — | Industrial (-40C to +100C Tj) |
| Supply Voltage (Core) | — | 0.9 V typical [DATA_NEEDED: full range from datasheet] |
| Configuration Method | — | FPGA configuration via Altera Quartus II |
| Hard IP Blocks | — | PCIe Gen2 hard IP, memory controllers, PLLs |
| Niveau MSL | — | 3 (per typical Altera FCBGA handling) |