EP2AGZ350HF40C3G vs EP2AGZ350HF40C2N Comparaison
Comparaison détaillée côte à côte de EP2AGZ350HF40C3G par Intel et EP2AGZ350HF40C2N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP2AGZ350HF40C3G - 350K LE Arria II GZ FPGA, 734 I/O, 1517-FBGA | Intel
EP2AGZ350HF40C3G ✓ Actif
Comparaison des spécifications
| Paramètre | EP2AGZ350HF40C3G | EP2AGZ350HF40C2N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 380,00 | $2 645,00 |
| Family | Arria II GZ | Arria II GZ |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 350,000 | — |
| Embedded Memory | [DATA_NEEDED: total embedded memory bits] | approximately 20 Mbits |
| DSP Blocks | [DATA_NEEDED: DSP block count and 18x18 multiplier count] | Dedicated 18x18 multipliers |
| User I/O Pins | 734 | — |
| Boîtier | 1517-ball FineLine BGA (HF40) | 1517-ball FCBGA (HF40), 40 mm x 40 mm |
| Package Pitch | 1.0 mm | — |
| Process Node | 40 nm | 40 nm low-power |
| Speed Grade | C3 (commercial, -3) | C2 (commercial) |
| Température de fonctionnement | Commercial (0C to 85C, suffix 0C) | 0C to +85C (commercial, per N suffix) |
| Transceivers | Up to 6.375 Gbps (channel count [DATA_NEEDED]) | Up to 16 channels |
| External Memory Interfaces | DDR3, DDR2, QDR II+ (up to 800 MHz) | — |
| PCI Express Hard Blocks | Yes (Gen1/Gen2) | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (FCBGA) |
| Statut RoHS | Compliant | Compliant (per product listing) |
| Lead-Free | Yes | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Logic Elements | — | 350,000 |
| Transceiver Data Rate | — | Up to 6.375 Gbps |
| I/O Standards | — | LVDS, LVCMOS, SSTL, HSTL, differential standards |
| External Memory Support | — | DDR3, QDR II+, RLDRAM II |
| Configuration Method | — | Quartus II design suite, JTAG, passive/active serial |