EP2C35F484C7 vs EP2C35F484I6N Comparaison
Comparaison détaillée côte à côte de EP2C35F484C7 par Intel et EP2C35F484I6N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2C35F484C7 | EP2C35F484I6N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $54,25 | $52,10 |
| Series | Cyclone II | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33,216 LE | 33,216 |
| Total Memory Bits | 483,840 bits | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Embedded Multipliers (18x18) | 35 | — |
| Maximum User I/O | 322 | — |
| Number of PLLs | 4 | — |
| Global Clock Networks | 16 | — |
| Process Technology | 90 nm CMOS, 1.2 V core | — |
| Core Voltage | 1.2 V | — |
| Température de fonctionnement | 0 C to 85 C (Commercial) | — |
| Boîtier | 484-pin FBGA (FineLine BGA) | 484-ball FBGA (Fine-Pitch BGA) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Configuration Modes | JTAG, Passive Serial (PS), Active Serial (AS) | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| External Memory Support | DDR, DDR2, QDRII SRAM | — |
| Lead-Free / RoHS | Lead-Free (per 'N' suffix not present; C7 = commercial temp) | — |
| Logic Array Blocks (LABs) | — | 2,100 |
| Total RAM Bits | — | 483,840 bits (483.84 Kbit on-chip) |
| Embedded 18x18 Multipliers | — | 35 (Cyclone II family maximum 150) |
| Phase-Locked Loops (PLLs) | — | 4 |
| Maximum User I/O Pins | — | 322 (package-dependent; FBGA-484 supports up to 322 user I/O) |
| Logic Family | — | CMOS |
| Core Supply Voltage | — | 1.2 V |
| Plage de température de fonctionnement | — | -40C to +85C (industrial) |
| Maximum Internal Clock Frequency | — | 402.5 MHz |
| Process Node | — | 90 nm TSMC CMOS |
| Statut RoHS | — | Compliant |
| Configuration Method | — | Serial / Parallel (via Altera/Intel configuration device or JTAG) |