EP2C8T144C7N vs EP2C8T144C6 Comparaison
Comparaison détaillée côte à côte de EP2C8T144C7N par Intel et EP2C8T144C6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2C8T144C7N | EP2C8T144C6 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $20,85 | $22,62 |
| Family | Cyclone II | Cyclone II |
| Logic Elements | 8256 | — |
| Embedded Memory (M4K blocks) | 165888 bits (36 M4K blocks) | — |
| Embedded 18x18 Multipliers | 36 | 18 |
| PLLs | 2 | 4 |
| Maximum User I/O | 85 | — |
| Boîtier | 144-LQFP (T144) 20x20 mm, 0.5 mm pitch | 144-pin LQFP (TQFP), 22x22 mm, 0.5 mm pitch |
| Process Node | 90 nm | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) | — |
| Maximum Internal Clock Frequency | approximately 450 MHz (speed grade 7) | — |
| Speed Grade | 7 (commercial) | 6 |
| Température de fonctionnement | 0C to +85C (commercial) | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Yes (N suffix) | — |
| Statut RoHS | Compliant | Non-compliant (per distributor listing) |
| Logic Elements (LE) | — | 8,256 |
| Configurable Logic Blocks (CLB) | — | 516 |
| Embedded Memory (bits) | — | 165,888 |
| Embedded RAM Blocks | — | 36 M4K blocks (4,608 bits each) |
| User I/O Pins (max) | — | 85 |
| Maximum User I/O (this package) | — | 85 |
| Process Technology | — | 90 nm CMOS |
| Core Voltage | — | 1.2 V (typical) |
| Plage de température de fonctionnement | — | Commercial (0C to +85C) |
| Configuration Interface | — | JTAG (IEEE 1149.1), Altera AS / PS / PP |
| Design Software | — | Quartus II (v13.0 SP1 recommended) |
| Maximum Internal Frequency | — | [DATA_NEEDED: see Cyclone II device handbook for fMAX by design] |