EP2S130F1020C3NRB vs EP2S130F1020C5N Comparaison
Comparaison détaillée côte à côte de EP2S130F1020C3NRB par Intel et EP2S130F1020C5N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP2S130F1020C3NRB - Stratix II FPGA, 132K LE, 742 I/O, 1020-BBGA
EP2S130F1020C3NRB ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EP2S130F1020C3NRB | EP2S130F1020C5N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 245,00 | $1 320,00 |
| Manufacturer | Intel Corporation (formerly Altera) | — |
| Series | Stratix II | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Logic Elements (LEs) | 132,540 | — |
| Total Memory | 6,748 Kbits | — |
| LABs/CLBs | 6,627 | — |
| User I/O Count | 742 | — |
| Boîtier | 1020-BBGA (33x33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (33x33 mm) |
| Température de fonctionnement | 0C to +85C (commercial, C3 speed grade) | Commercial (0C to +85C, C5 grade) |
| Process Node | 90 nm | — |
| Type de montage | Surface Mount | Surface Mount |
| Lead Free / RoHS Status | Lead Free / RoHS Compliant | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Voltage - Supply (VCCINT) | [DATA_NEEDED: VCCINT nominal] | — |
| Voltage - I/O Banks | [DATA_NEEDED: VCCIO range] | — |
| Family | — | Stratix II |
| Logic Elements | — | 132,540 |
| Adaptive Logic Modules (ALMs) | — | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | — | 6,747,840 bits |
| User I/Os | — | 734 |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperature Grade | — | C5 (other - per Partstack) |
| Statut RoHS | — | [DATA_NEEDED: rohs status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |