EP2S130F1020C4 vs EP2S60F1020C4N Comparaison
Comparaison détaillée côte à côte de EP2S130F1020C4 par Intel et EP2S60F1020C4N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S130F1020C4 | EP2S60F1020C4N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 800,00 | $67,00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Logic Elements | 132,540 | 60,440 |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Boîtier | 1020-ball FC-FBGA | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| User I/O Count | 742 | — |
| Maximum Internal Frequency | 711.24 MHz | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | Commercial (0C to +85C) - grade 'C' | — |
| Speed Grade | C4 | — |
| Type de mémoire | Embedded SRAM blocks (Stratix II) | — |
| DSP Blocks | Embedded multipliers (Stratix II TriMatrix) | — |
| PLLs | Yes (Stratix II enhanced PLL + fast PLL) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | EU RoHS compliant with exemption (per Arrow listing) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | Stratix II |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |