EP2S130F1508C5 vs EP2S130F1508C3 Comparaison
Comparaison détaillée côte à côte de EP2S130F1508C5 par Altera et EP2S130F1508C3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP2S130F1508C5 - Stratix II FPGA, 132K LEs, 1508-FBGA | Intel / Altera
EP2S130F1508C5 ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EP2S130F1508C5 | EP2S130F1508C3 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $345,00 | $1 350,00 |
| Series | Stratix II | — |
| Manufacturer | Intel / Altera | — |
| Logic Elements / Cells | 132,540 | — |
| Logic Array Blocks (LABs) | 6,627 | — |
| Number of CLBs | 53,016 | — |
| User I/O Count | 1,126 | — |
| Embedded Memory (Bits) | 6,747,840 (approx. 6.7 Mbit) | — |
| Embedded 18x18 Multipliers | 252 | — |
| Core Voltage | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm CMOS | 90 nm |
| Speed Grade | C5 (commercial) | C3 (commercial) |
| Boîtier / Format | 1508-BBGA, FCBGA (FineLine BGA) | — |
| Package Dimensions | 40 x 40 mm | — |
| Ball Pitch | 1.0 mm | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Température de fonctionnement | Commercial (0 C to +85 C) | 0C to +85C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Family | — | Stratix II |
| Logic Elements | — | 132,540 |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory (bits) | — | 6,747,840 |
| Maximum User I/O | — | 1,126 |
| Core Voltage (typical) | — | 1.2 V |
| Boîtier | — | 1508-ball FC-BGA |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceivers | — | [DATA_NEEDED: transceiver count/grade] |
| PLLs (Fast + Enhanced) | — | 8 + 4 (per family) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |