EP2S15F484C5N vs EP2S15F484C4 Comparaison
Comparaison détaillée côte à côte de EP2S15F484C5N par Intel et EP2S15F484C4 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S15F484C5N | EP2S15F484C4 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $144,80 | $205,00 |
| Family | Stratix II | Stratix II |
| Logic Elements (LEs) | 15,600 | 15,600 |
| Embedded RAM | 419 Kbits | — |
| Maximum User I/O | 342 | 342 |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Yes (integrated multiplier-accumulators) |
| Process Technology | 90 nm | 90 nm CMOS |
| Boîtier | 484-ball FineLine BGA (FBGA) | 484-FBGA (FBGA-484) |
| Speed Grade | C5 | C4 (-4, mid-tier) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Configuration Modes | AS, PS, JTAG | — |
| Supply Voltage - Core (VCCINT) | [DATA_NEEDED: VCCINT nominal] | — |
| Supply Voltage - I/O (VCCIO) | [DATA_NEEDED: VCCIO nominal] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| External Memory Support | DDR/DDR2 SDRAM, QDR II SRAM | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free FBGA package) |
| Type de montage | Surface Mount | — |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Adaptive Logic Modules (ALMs) / CLBs | — | 6,240 |
| Embedded Memory (Bits) | — | 419,328 |
| Package Dimensions | — | 23 mm x 23 mm |
| Ball Pitch | — | 1.0 mm |
| Core Performance | — | Up to 717 MHz |
| Temperature Grade | — | Commercial (C): 0 C to +85 C junction |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT nominal] |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| External Memory Interface | — | DDR, DDR2, QDR SRAM |
| Configuration Method | — | Serial/parallel, JTAG |