EP2S30F672C5NRB vs EP2S30F672I4 Comparaison
Comparaison détaillée côte à côte de EP2S30F672C5NRB par Intel et EP2S30F672I4 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S30F672C5NRB | EP2S30F672I4 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $180,00 | $695,00 |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Logic Elements / Cells | 33,880 | — |
| Number of LABs / CLBs | 1,694 | — |
| Total RAM Bits | [DATA_NEEDED: total embedded memory bits] | 1369728 |
| Number of I/O | 500 | 500 |
| Voltage - Supply (Core) | 1.15 V to 1.25 V | — |
| Type de montage | Surface Mount | Surface Mount |
| Boîtier / Format | 672-BBGA | 672-BBGA, FCBGA (FBGA-672) |
| Supplier Device Package | 672-FBGA (27 x 27 mm) | — |
| Température de fonctionnement | 0 C to 85 C (TJ) | -40C to +100C (Industrial) |
| Packaging | Tray (NRB suffix = RoHS, no NRB = legacy) | — |
| Process Technology | 90 nm CMOS, SRAM-based configuration | 90 nm CMOS |
| Configuration Method | SRAM, configured via JTAG, PS, or FPP | — |
| Statut RoHS | Compliant (NRB suffix) | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Product Status | Obsolete (last time buy / end of life) | — |
| Logic Elements | — | 33880 |
| Logic Array Blocks (LABs) | — | 1694 |
| DSP Blocks | — | 12 (per datasheet, family range) |
| Number of PLLs | — | 6 |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |
| Niveau MSL | — | 3 (per JEDEC J-STD-020) |