EP2S60F1020C4 vs EP2S60F1020C4N Comparaison
Comparaison détaillée côte à côte de EP2S60F1020C4 par Intel et EP2S60F1020C4N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F1020C4 | EP2S60F1020C4N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 240,00 | $67,00 |
| Series | Stratix II | Stratix II |
| Logic Elements | 60,440 LE | 60,440 |
| Total Memory Bits | 2,544,192 bits | — |
| Number of LABs | 3022 | — |
| Number of User I/O | 718 | — |
| Number of Embedded Multipliers | [DATA_NEEDED: number of 18x18 multipliers] | — |
| Number of PLLs | [DATA_NEEDED: number of PLLs/DLLs] | — |
| Core Voltage | 1.2 V | 1.2 V |
| Maximum Operating Frequency | 711.24 MHz | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Speed Grade | -C4 (commercial) | — |
| Température de fonctionnement | 0C to +85C (commercial) | — |
| Boîtier | 1020-ball FC-FBGA (FineLine BGA) | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Statut RoHS | Compliant (lead-free per Intel/Altera product page) | EU RoHS compliant with exemption (per Arrow listing) |
| Family | — | Stratix II (EP2S60) |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | — | 718 |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Operating Temperature Grade | — | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |