EP2S60F484I5N vs EP2S60F484I4 Comparaison
Comparaison détaillée côte à côte de EP2S60F484I5N par Altera et EP2S60F484I4 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F484I5N | EP2S60F484I4 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 325,00 | $138,40 |
| Series | Stratix II (EP2S60) | Stratix II |
| Family | Field Programmable Gate Array (FPGA) | Stratix II FPGA |
| Logic Elements (LE) | 60,440 | 60,440 |
| Adaptive Logic Modules (ALM) | 24,176 | [DATA_NEEDED: ALM count] |
| Embedded Memory (bits) | 2,544,192 | — |
| Embedded Memory (M512/M4K/M-RAM blocks) | M512: 330, M4K: 255, M-RAM: 2 | — |
| DSP Blocks (18-bit multipliers) | 48 blocks (192 18x18 multipliers) | — |
| PLLs | 12 (4 enhanced + 8 fast) | 4 |
| Maximum User I/O Pins | 334 | — |
| Maximum Fabric Clock | 609.76 MHz | — |
| Core Supply Voltage | 1.2 V typical | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Boîtier | 484-ball FC-FBGA (Flip-Chip Fine-pitch BGA), 1.00 mm pitch | 484-ball FBGA (F484) |
| Speed Grade | I5 (industrial, slow-speed for low power) | I4 (industrial, fastest speed bin for Stratix II F484) |
| Plage de température de fonctionnement | -40 °C to +100 °C (industrial) | -40 °C to +100 °C (Industrial, I4) |
| Type de montage | Surface Mount (BGA) | Surface Mount |
| Statut RoHS | [DATA_NEEDED: rohs status not stated in verified data] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free / halogen-free status] | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel | — |
| Design Tool | Quartus II (legacy; current Intel Quartus Prime with Stratix II device support) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Embedded Memory Bits | — | 2,544,192 bits (~317 KB) |
| Total RAM Blocks | — | [DATA_NEEDED: total RAM blocks] |
| User I/O Pins | — | 334 |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| High-Speed Transceivers | — | 12 channels |
| Transceiver Data Rate | — | [DATA_NEEDED: max Gbps] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Core Voltage | — | 1.2 V |
| Ball Pitch | — | [DATA_NEEDED: ball pitch in mm] |
| Lead-Free / RoHS | — | Contains Lead; RoHS Non-Compliant (per distributor data) |
| Configuration Method | — | SRAM-based, loaded via Quartus II bitstream |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |