EP2S60F672C5 vs EP2S60F672C5N Comparaison
Comparaison détaillée côte à côte de EP2S60F672C5 par Intel et EP2S60F672C5N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S60F672C5 | EP2S60F672C5N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $410,85 | $170,00 |
| Family | Stratix II | Stratix II |
| Device Family | Stratix II FPGA | — |
| Logic Elements | 60,440 | — |
| Configurable Logic Blocks (CLBs) | 24,176 | — |
| Total RAM Bits | 2,544,192 bits | — |
| Maximum User I/Os | 492 | 492 |
| Operating Frequency | Up to 609.76 MHz | — |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | 90 nm |
| Boîtier | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) | 672-ball FC-FBGA |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) | — |
| Plage de température de fonctionnement | 0°C to +85°C | — |
| Number of PLLs | 4 | — |
| DSP Blocks | 12 (dedicated 18 × 18 multipliers) | — |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | — |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | — |
| Statut RoHS | Non-RoHS (legacy product, pre-RoHS production runs) | Non-compliant (contains lead, per Altera/Intel EOL notice) |
| Logic Elements (LEs) | — | 60440 |
| Logic Array Blocks (LABs) | — | 3022 |
| Embedded Memory (bits) | — | 2544192 |
| Core Voltage (VCCINT) | — | 1.2 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Speed Grade | — | C5 (commercial) |
| Temperature Grade | — | Commercial |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Configuration Memory | — | SRAM-based (volatile, requires external configuration device) |