EP2S90F1020C4N vs EP2S60F1020C4N Comparaison
Comparaison détaillée côte à côte de EP2S90F1020C4N par Intel et EP2S60F1020C4N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2S90F1020C4N | EP2S60F1020C4N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 320,00 | $67,00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Logic Elements (LEs) | 90,960 | — |
| LABs/CLBs | 4,548 | — |
| Total Memory Bits | 4,520,488 | — |
| User I/Os | 758 | 718 |
| Nombre de broches | 1020 | — |
| Package Type | FC-FBGA (Flip-Chip Fine-pitch BGA) | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Maximum Fabric Frequency | 711.24 MHz | — |
| Operating Temperature Grade | Commercial (C4 suffix) | Commercial (C4 suffix indicates commercial, speed grade 4) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Configuration Method | JTAG / Passive Serial / Passive Parallel / Active Serial | — |
| Statut RoHS | Compliant | EU RoHS compliant with exemption (per Arrow listing) |
| Statut du cycle de vie | Not Recommended for New Designs (NRND) | — |
| Series | — | Stratix II |
| Logic Elements | — | 60,440 |
| Adaptive Logic Modules (ALMs) | — | 30,220 (approx.) |
| Logic Array Blocks (LABs) | — | 3,022 |
| Embedded Memory (bits) | — | 2,544,192 |
| Embedded Memory Blocks | — | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | — | Up to 48 (24 per DSP block column pair typical) |
| Maximum Core Frequency | — | 711.24 MHz (per Arrow listing) |
| Boîtier | — | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs / Clock Networks | — | Yes - on-chip PLLs and global clock networks |