EP2SGX130GF1508C3N vs EP2SGX130GF40I4GA Comparaison
Comparaison détaillée côte à côte de EP2SGX130GF1508C3N par Intel et EP2SGX130GF40I4GA par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP2SGX130GF1508C3N - Stratix II GX FPGA, 132K LEs, 20x Transceivers | Intel
EP2SGX130GF1508C3N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP2SGX130GF1508C3N | EP2SGX130GF40I4GA |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 395,00 | $3 600,00 |
| Series | Stratix II GX | — |
| Family | FPGA - Field Programmable Gate Array | Stratix II GX |
| Logic Elements | 132,540 | 132,540 |
| Logic Array Blocks (LABs) | 6,627 | 6,627 |
| User I/Os | 734 | — |
| Total RAM Bits | 6,747,840 (approximately 6.75 Mbit) | — |
| Number of Transceivers | 20 | — |
| Transceiver Data Rate (max) | 6.375 Gbps | — |
| Number of 18x18 Multipliers | 56 | — |
| Number of PLLs | 12 | — |
| Internal Fabric Clock (max) | 717 MHz | — |
| Memory Clock (max) | 717 MHz | — |
| Core Supply Voltage | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm CMOS | 90 nm |
| Operating Temperature Range (TJ) | 0 °C to 85 °C (commercial) | — |
| Boîtier | 1508-ball FBGA (FCBGA), 40 x 40 mm, 1.0 mm pitch | 1508-ball FCBGA (Fine-pitch Ball Grid Array) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Lead-free / RoHS Compliant | [DATA_NEEDED: confirm per data] |
| Estimated EOL Date | 2023 (per GlobalSpec listing) | — |
| Total Memory Bits | — | 6,747,840 |
| Dedicated Input Pins | — | 734 |
| Dedicated Output Pins | — | 734 |
| Transceivers | — | Up to 20 (multi-gigabit, 600 Mbps to 6.375 Gbps) |
| Ball Pitch | — | 1.00 mm |
| Operating Temperature Grade | — | Industrial |
| Tension d'alimentation | — | [DATA_NEEDED: core and I/O rail voltages] |
| Configuration Method | — | JTAG or Altera configuration device |