EP3SL200F1517I4L vs EP3SL200F1517I4LN Comparaison
Comparaison détaillée côte à côte de EP3SL200F1517I4L par Altera et EP3SL200F1517I4LN par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP3SL200F1517I4L - 200K LE Stratix III L FPGA, 1517-FCBGA | Altera
EP3SL200F1517I4L ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP3SL200F1517I4L | EP3SL200F1517I4LN |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $2 280,00 | $6 300,00 |
| Logic Elements | 200,000 | 200,000 |
| Logic Array Blocks (LABs) | 8,000 | 8,000 |
| Embedded Memory (bits) | 10,901,504 | — |
| User I/Os | 976 | — |
| Number of Pins / Balls | 1517 | — |
| Boîtier | 1517-BBGA, FC-FBGA (Flip-Chip) | 1517-BBGA, FCBGA |
| Core Voltage | 0.9 V | — |
| Process Node | 65 nm CMOS | — |
| Speed Grade | I4 (industrial, speed grade 4) | — |
| Température de jonction en fonctionnement | -40C to +100C | — |
| Family | Stratix III L (logic-optimized) | Stratix III L |
| DSP Blocks / 18x18 Multipliers | 384 (18x18) | — |
| Transceivers | [DATA_NEEDED: transceiver count and max data rate] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | — |
| Type de montage | Surface Mount (BGA) | Surface Mount (BGA) |
| Statut RoHS | [DATA_NEEDED: per batch] | Compliant |
| Niveau MSL | [DATA_NEEDED: per package datasheet] | [DATA_NEEDED: MSL moisture sensitivity level] |
| Embedded Memory Bits | — | 10,901,504 |
| User I/O Pins | — | 976 |
| Process Technology | — | 65 nm TSMC low-power |
| Température de fonctionnement | — | -40C to +100C (Industrial) |
| Lead-Free | — | Yes |
| Supply Voltage Core | — | [DATA_NEEDED: VCC core voltage] |
| Transceiver Data Rate (max) | — | [DATA_NEEDED: max transceiver rate] |
| DSP Blocks (18x18 multipliers) | — | 384 |
| DSP Performance | — | 288 GMACS |
| Configuration Method | — | Passive Parallel / Active Serial / JTAG |
| Ball Pitch | — | 1.0 mm |
| Package Dimensions | — | 40 mm x 40 mm |