EP3SL50F484C3 vs EP3SL50F484C2 Comparaison
Comparaison détaillée côte à côte de EP3SL50F484C3 par Intel et EP3SL50F484C2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP3SL50F484C3 | EP3SL50F484C2 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $478,80 |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA |
| Family | Stratix III L | Stratix III L (low-power) |
| Logic Cells | 47,500 cells | — |
| Technology | 65 nm | — |
| Listed Frequency | 500 MHz | — |
| Internal Frequency | 800 MHz | — |
| Tension d'alimentation | 1.1 V | — |
| Logic Array Blocks | 1,900 LABs | — |
| User I/O | 296 I/Os | — |
| Boîtier | 484-pin FC-FBGA | 484-BBGA, FCBGA (FineLine BGA) |
| Nombre de broches | 484 pins | — |
| Package Type | FBGA-484 | — |
| Température de fonctionnement | 0 °C to 85 °C | 0 C to 85 C (commercial) |
| Device Category | Programmable logic IC | — |
| Type de montage | Surface Mount | Surface Mount |
| Manufacturer Technology Description | 65-nm low-power high-performance FPGA | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory size] | SRAM-based (volatile, requires external flash/EPC) |
| Embedded Transceivers | [DATA_NEEDED: embedded transceiver count] | — |
| Power Consumption | [DATA_NEEDED: power consumption] | — |
| Logic Elements | — | 47,500 |
| Logic Array Blocks (LABs) | — | 1,900 |
| Embedded Memory Bits | — | 2,184,192 |
| Maximum Internal Frequency | — | 800 MHz |
| User I/O Pins | — | 296 |
| Process Technology | — | 40 nm CMOS (TSMC) |
| Core Supply Voltage | — | 0.9 V |
| Lead-Free | — | Yes |
| Speed Grade | — | C2 (slower of Stratix III commercial) |