EP610DC-15 vs EP610DC-10 Comparaison
Comparaison détaillée côte à côte de EP610DC-15 par Altera et EP610DC-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC-15 | EP610DC-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,95 | $7,95 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Température de fonctionnement | 0C to 70C (commercial) | 0C to +70C (commercial) |
| Boîtier | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP, windowed) |
| Type de montage | Through-Hole | Through-Hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | CMOS, EPROM-based (UV-erasable) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified web data] |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Tension d'alimentation | — | 5 V (single supply) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |