EP610ILC-10 vs EP610DC-10 Comparaison
Comparaison détaillée côte à côte de EP610ILC-10 par Altera et EP610DC-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610ILC-10 | EP610DC-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,20 | $7,95 |
| Device Family | Classic EPLD | Altera Classic EPLD |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Dedicated Inputs | 4 | — |
| Tension d'alimentation | 5 V (single supply) | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Boîtier | PLCC-28 (plastic J-lead chip carrier) | 24-pin CDIP (Ceramic DIP, windowed) |
| Type de montage | Surface Mount (PLCC socket or solder) | Through-Hole |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified web data] |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Technology | — | CMOS, EPROM-based (UV-erasable) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |