EP610LI-25 vs EP610PC-25T Comparaison
Comparaison détaillée côte à côte de EP610LI-25 par Rochester Electronics et EP610PC-25T par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP610LI-25 - 16-Macrocell Classic EPLD, 25ns, CMOS | Altera / Rochester Electronics
EP610LI-25 ✓ ActifIntel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP610LI-25 | EP610PC-25T |
|---|---|---|
| Marque | Rochester Electronics | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,25 | $28,95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Speed Grade | 25 (25 ns tPD) | — |
| Power Variant | L (low-power CMOS) | — |
| Temperature Grade | I (industrial) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| Technology | CMOS, UV-erasable (windowed) | — |
| Boîtier | Ceramic DIP-24 (windowed, Altera 'I' designation) | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) |
| Type de montage | Through-hole | Through-hole |
| Programming Method | Altera MAX+PLUS II / Classic compiler + compatible programmer | OTP (one-time programmable) via Altera programming hardware |
| Statut RoHS | Unknown - ceramic DIP legacy package | [DATA_NEEDED: RoHS status] |
| Manufacturer / Source | Altera (original), Rochester Electronics (authorized continuing supplier) | — |
| Manufacturer | — | Intel (formerly Altera) |
| Distributor / Stocking Source | — | Rochester Electronics, LLC |
| Device Family | — | Altera Classic EPLD - EP610 |
| Device Type | — | Erasable Programmable Logic Device (EPLD, OTP for plastic package) |
| Logic Capacity | — | 300 usable gates |
| Macro Cells | — | 16 |
| Registers | — | 16 |
| User I/Os | — | 16 |
| Propagation Delay (tPD) | — | 25 ns (speed grade 25) |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fmax] |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | ECMOS (CMOS, EPROM-based) |
| Pinout Compatibility | — | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) |
| Température de fonctionnement | — | 0 °C to +70 °C (commercial) |
| Shipping Form (T suffix) | — | Tube |