EP610PC-25T vs EP610DC-25 Comparaison
Comparaison détaillée côte à côte de EP610PC-25T par Intel et EP610DC-25 par Rochester Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Dernier achatRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActifComparaison des spécifications
| Paramètre | EP610PC-25T | EP610DC-25 |
|---|---|---|
| Marque | Intel | Rochester Electronics |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,95 | $9,95 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Boîtier | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | 0 C to +70 C |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | JEDEC fuse-map / UV-erase |
| Type de montage | Through-hole | Through Hole |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |