EP610PC-25T vs EP610PI-25 Comparaison
Comparaison détaillée côte à côte de EP610PC-25T par Intel et EP610PI-25 par Rochester Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Dernier achatRochester Electronics
EP610PI-25 - 16-Macrocell Classic EPLD, 25ns DIP-24 | Rochester
EP610PI-25 ObsoleteComparaison des spécifications
| Paramètre | EP610PC-25T | EP610PI-25 |
|---|---|---|
| Marque | Intel | Rochester Electronics |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,95 | $20,50 |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | 25 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V nominal |
| Process Technology | ECMOS (CMOS, EPROM-based) | CMOS, UV-erasable |
| Boîtier | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin DIP (PI) ceramic through-hole |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | — |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Type de montage | Through-hole | Through-Hole (DIP) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Shipping Form (T suffix) | Tube | — |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Series | — | Classic EP610 |
| Macrocells | — | 16 |
| Usable Gates | — | ~300 gates |
| Maximum Internal Frequency (fCNT) | — | [DATA_NEEDED: fCNT] |
| Number of Dedicated Inputs | — | 4 |
| Number of Bidirectional I/O Pins | — | 16 |
| Plage de température de fonctionnement | — | Industrial (I suffix): -40C to +85C |
| Programmable Flip-Flop Modes | — | D, T, JK, SR (per macrocell) |
| Global Clock Pins | — | 1 |
| Lead-Free / RoHS | — | [DATA_NEEDED: RoHS] |
| Original Manufacturer | — | Altera (now Intel PSG; legacy stock from Rochester Electronics) |