EP910DC-15 vs EP910ILC-12 Comparaison
Comparaison détaillée côte à côte de EP910DC-15 par Altera et EP910ILC-12 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910DC-15 | EP910ILC-12 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,75 | $12,40 |
| Family | Altera Classic EPLD | Altera EP910 Classic EPLD |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V |
| Température de fonctionnement | 0C to +70C (commercial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Technology | CMOS EPROM, UV-erasable | — |
| Boîtier | 24-pin ceramic DIP (DC) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Type de montage | Through-Hole | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Statut RoHS | [DATA_NEEDED: not explicitly stated in verified data] | [DATA_NEEDED: RoHS status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 (typical) |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| Nombre de broches | — | 28 |
| Feedback Paths | — | 16 dedicated |