EP910DI-30 vs EP910DC-30 Comparaison
Comparaison détaillée côte à côte de EP910DI-30 par Rochester Electronics et EP910DC-30 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndComparaison des spécifications
| Paramètre | EP910DI-30 | EP910DC-30 |
|---|---|---|
| Marque | Rochester Electronics | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,60 | $15,60 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD (EP910 series) |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | CDIP-40 (ceramic DIP, 40-pin with UV window) | DIP-40 (through-hole, 600 mil) |
| Type de montage | Through-Hole (DIP) | Through-Hole |
| Dedicated Inputs | 10 | 36 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Nombre de broches | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Température de fonctionnement | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tension d'alimentation | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |