EP910DI-35 vs EP910DI-30 Comparaison
Comparaison détaillée côte à côte de EP910DI-35 par Altera et EP910DI-30 par Rochester Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndComparaison des spécifications
| Paramètre | EP910DI-35 | EP910DI-30 |
|---|---|---|
| Marque | Altera | Rochester Electronics |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $35,20 | $17,60 |
| Product Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | Classic EPLD (Altera EP910 series) |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 10 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| Boîtier | CDIP-40 (Ceramic DIP with UV window) | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Température de fonctionnement | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| Programming Method | EPROM programmer + JEDEC fuse map | — |
| Erasure Method | UV light through quartz window | — |
| Statut RoHS | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Macrocell Count | — | 24 |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| Nombre de broches | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |